1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device equipped with a dynamic latch type sense amplifier which amplifies complementary signals. The dynamic latch type sense amplifier is configured as follows. The potentials of capacitances coupled to a pair of bit lines connected to a cell (memory element) are set equal to each other before data is read from the cell. When the data is read from the cell, the fine potential difference between the pair of bit lines is amplified by a flip-flop type circuit, and amplified data is output.
Recently, it has been required that the semiconductor memory devices such as SRAM (Static Random Access Memory) devices have a reduced cell data read time and a reduced power consumption as the electronic devices equipped with the semiconductor memory devices have advanced performance.
2. Description of the Related Art
A conventional semiconductor device will be described with reference to FIGS. 1, 2 and 3.
FIG. 1 is a block diagram illustrating the overall structure of an SRAM device.
The SRAM device is equipped with a memory cell array 10, a row address buffer 12, a row decoder 14, a word driver 16, a column address buffer 18, a column decoder 20, a column select switch 22, a sense amplifier 24C, an input/output data control circuit 26, a chip enable buffer 28, a write enable buffer 30, a precharge power source 32C and a timing generator 33. The memory cell array 10 has memory elements or cells that are arranged in a matrix formation and function to store data in static fashion.
A row address signal and a column address signal are temporarily stored in the row address buffer 12 and the column address buffer 18, respectively, and are then output to the row decoder 14 and the column decoder 20.
The decoded row address signal is input to the word driver 16. and the decoded column signal is input to the column select switch 22. Thus, the cell specified by the row and column addresses is selected from among the cells of the memory cell array 10. Then, data is read from or written into the selected cell. At that time, the sense amplifier 24C functions to amplify the data read from the selected cell. The amplified data signal is output via the input/output data control circuit 26.
A chip enable signal selects one of a plurality of SRAM devices (chips) which configure a memory system. When the SRAM devices are set to be in the non-selected or disabled states by the respective chip enable signals, all the internal circuits of the SRAM devices are in the disabled states. Hence, power consumed in the memory system can be reduced. A write enable signal is an external input signal that controls a data write/read operation on the memory cell array 10.
The chip enable signal and the write enable signals are input to the input/output data control circuit 26 via the chip enable buffer 28 and the write enable buffer 30, respectively. The precharge power source 32C is connected to the sense amplifier 24C, and sets the sense amplifier 24C to a given potential VCCH (precharge potential).
The timing generator 33 generates reference or timing signals used to pull the operation timings of the circuits in the SRAM device in phase. The reference signals are generated by a synchronizing signal externally supplied to the SRAM device, and are then applied to, for example, the buffers and sense amplifier 24C.
Next, the sense amplifier 24C will be described with reference to FIGS. 2 and 3.
FIG. 2 exemplary shows the sense amplifier 24C and a cell (cell C) connected to a pair of bit lines BLX and BLZ. The sense amplifier 24C includes n-channel MOS (Metal Oxide Semiconductor) transistors Q1, Q2, Q3 and Q4. The cell C includes p-channel MOS transistors P7 and P8 and nMOS transistors Q7, Q8, Q9 and Q10.
The precharge power source 32C applies a potential VCC-PC (for example, 1.5 V) to the sense amplifier 24C. The transistors P1 and P2 connected to the precharge power source 32C are used to precharge the bit lines BLX and BLZ, respectively. A precharge control signal PCZ generated by the timing generator 33 is applied to the gates of the transistors P1 and P2.
The gates of the transistors Q1 and Q2 are connected to the drains of the transistors Q2 and Q1, respectively, and form a flip-flop circuit. The sources of the transistors Q1 and Q2 are respectively connected to nodes NX and NZ.
The transistors Q3 and Q4 function as pull-down transistors in which the sources thereof are set at the ground potential GND. The transistors Q5 and Q6 function as charge transfer transistors in which the drains thereof are connected to output terminals OUTX and OUTZ and the sources thereof are connected to the bit lines BLX and BLZ, respectively.
The output terminals OUTX and the OUTZ are connected to the input/output data control circuit 26 shown in FIG. 1. The gates of the transistors Q3 and Q4 are supplied with a sense enable signal Enx from the timing generator 33 shown in FIG. 1. The gates of the transistors Q5 and Q6 are supplied with a column select signal CLx from the column decoder 20 shown in FIG. 1.
The gates of the transistors P5 and P6 are supplied with a bit line reset signal BLRST generated by the timing generator 33. When the bit line reset signal BLRST is at the ground potential GND, the transistors P5 and P6 are turned on and the bit lines BLX and BLZ are reset to the potential VCC.
The cell C is made up of the transistors P7, Q7, P8 and Q8 which form a flip-flop circuit, and nMOS transistors Q9 and Q10 for use in the read/write operations. The signal transferred over the word line WL is applied to the gates of the transistors Q9 and Q10. When the transistors Q9 and Q10 are turned on, the potential of the bit line BLX or BLZ is pulled down in accordance with the state of the flip-flop circuit. Hence, data stored in the cell C can be read. The potential difference between the bit lines BLX and BLZ is amplified by the sense amplifier 24C. When a large amplitude of the bit line potential difference is applied through the transistors Q9 and Q10, data can be written into the flip-flop circuit.
After a standby period, the sense amplifier 24C charges the capacitances coupled to the bit lines BLX and BLZ during a precharge period. After that, the signal on the word line is applied to the cell C during a cell read period, and the data is read from the cell C. The read data is amplified by the sense amplifier 24C during a sense period.
FIG. 3 shows the above-mentioned cycle, in which voltages and signals are illustrated to describe the operation of the sense amplifier 24C shown in FIG. 2.
During the standby period, the precharge control signal PCZ is at the ground level GND, and the pMOS transistors P1 and P2 for use in precharging are on. Hence, the output terminals OUTX and OUTZ are precharged to the potential VCCH.
During the precharge period following the standby period, the gates of the pMOS transistors P5 and P6 are supplied with the bit line reset signal BLRST of the potential VCC (high level) to which the bit lines BLX and BLZ are reset. Hence, the transistors P5 and P6 are off.
At that time, the column select signal CLx of the high-level potential VCCH (&gt;VCC) is applied to the gates of the nMOS transistors QS and Q6, which are thus turned on. Hence, the bit lines BLX and BLZ are charged via the transistors Q5 and Q6 from the transistors P1 and P2. In that manner, the bit lines BLX and BLZ are precharged. The potentials of the bit lines BLX and BLZ after the precharging are lower than the potential VCCH by the threshold voltages Vth of the transistors Q5 and Q6.
During the cell read period, the precharge control signal PCZ is set to the potential VCCH (high level) so that the transistors P1 and P2 are turned off. At that time, when the signal of the potential VCCH (high level) is transferred over the word line WL, the transistor Q9 and Q10 are turned on, and the potential of one of the bit lines BLX and BLZ (for example, BLZ) is pulled down.
When the potential of the bit line BLZ is decreased, the gate-source voltage VGS of the transistor Q6 having the source connected to the bit lie BLZ becomes greater than the threshold voltage Vth (VGS&gt;Vth), the transistor Q6 is turned on. Hence, the drain (OUTZ) of the transistor Q6 that was potentially in the floating state is decreased. At that time, the gate-source voltage VGS of the transistor Q5 is approximately equal to the threshold voltage Vth, and is approximately off. Hence, the output terminal OUTX is maintained at the potential VCCH previously precharged.
The potential difference between the output terminals OUTX and OUTZ becomes larger than the difference (approximately equal to 0.1 V) between the threshold voltages Vth by reading the data from the cell.
During the sense period, the gates of the nMOS transistors Q3 and Q4 for use in the pull-down operation are supplied with the sense enable signal Enx of the potential VCC (high level). Hence, the transistors Q3 and Q4 are turned on. At that time, the column select signal CLx is set to the ground potential GND, and the transistors Q5 and Q6 are turned off. Hence, the bit lines BLX and BLZ are electrically isolated.
Since the potential difference between the output terminals OUTX and OUTZ is already set equal to or greater than the mismatch value of the threshold voltages Vth of the transistors Q1 and Q2 during the cell read period, the dynamic latch formed of the transistors Q1 and Q2 is activated when the transistors Q3 and Q4 are turned on. Hence, a current flows in a route including the output terminal OUTZ, the transistor Q2 and the transistor Q4 in this order. Thus, the output terminal OUTZ is decreased to the ground potential GND. The gate potential of the transistor Q1 is decreased and is thus retained in the off state, and the potential of the output terminal OUTX is kept high.
As described above, the sense amplifier 24C precharges the bit lines BLX and BLZ and thus sets the gate-source voltages VGS of the transistors Q5 and Q6 to be approximately equal to the threshold voltages Vth. Additionally, the flip-flop circuit causes the potential difference between the output terminals OUTX and OUTZ to be equal to or greater than the mismatch value of the threshold voltages Vth of the transistors Q1 and Q2. Then, the potential latch is carried out. Thus, the potential differences between the transistors Q1 and Q2 and between the transistors Q5 and Q6 can be compensated for.
It takes about 10 ns to precharge the bit lines BLX and BLZ by setting, in the precharge period, the potential of the column select signal CLx to the high level so that the charge transfer gates Q5 and Q6 are turned on. This prevents the total operation time from being reduced. Further, since the potential of the precharge power source 32C is always maintained at the potential VCCH (&gt;VCC), there are the potential differences between the output terminals OUTX and OUTZ and between the bit lines BLX and BLZ even during the standby period and the sense period in which periods the charge transfer gates Q5 and Q6 are closed. The above potential differences result in a fine leakage current, which increases power consumption of the semiconductor device.